[Target] Use llvm::append_range (NFC) #135568
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-backend-arm Author: Kazu Hirata (kazutakahirata) ChangesFull diff: https://github.com/llvm/llvm-project/pull/135568.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 6bf6ce7167833..68218e59961c2 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3980,7 +3980,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
}
if (!InsertBeforeLR)
- CSI.insert(CSI.end(), VGSaves.begin(), VGSaves.end());
+ llvm::append_range(CSI, VGSaves);
}
Register LastReg = 0;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 356040da95672..bd95bcd89e183 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4055,8 +4055,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
}
if (IsChainCallConv)
- Ops.insert(Ops.end(), ChainCallSpecialArgs.begin(),
- ChainCallSpecialArgs.end());
+ llvm::append_range(Ops, ChainCallSpecialArgs);
// Add argument registers to the end of the list so that they are known live
// into the call.
@@ -15526,9 +15525,9 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// Adjust the writemask in the node
SmallVector<SDValue, 12> Ops;
- Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
+ llvm::append_range(Ops, Node->ops().take_front(DmaskIdx));
Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
- Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
+ llvm::append_range(Ops, Node->ops().drop_front(DmaskIdx + 1));
MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
index ec11a78f8a7af..9d35626f449de 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
@@ -14,6 +14,7 @@
#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include <cstddef>
#include <cstdint>
@@ -60,7 +61,7 @@ class UnwindOpcodeAssembler {
/// Emit unwind raw opcodes
void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) {
- Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end());
+ llvm::append_range(Ops, Opcodes);
OpBegins.push_back(OpBegins.back() + Opcodes.size());
}
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
index 156b40eb43a3e..68b24dbe9f006 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
@@ -55,7 +55,7 @@ void WebAssemblyAsmTypeCheck::funcDecl(const wasm::WasmSignature &Sig) {
void WebAssemblyAsmTypeCheck::localDecl(
const SmallVectorImpl<wasm::ValType> &Locals) {
- LocalTypes.insert(LocalTypes.end(), Locals.begin(), Locals.end());
+ llvm::append_range(LocalTypes, Locals);
}
void WebAssemblyAsmTypeCheck::dumpTypeStack(Twine Msg) {
@@ -357,8 +357,7 @@ bool WebAssemblyAsmTypeCheck::checkTryTable(SMLoc ErrorLoc,
Opcode == wasm::WASM_OPCODE_CATCH_REF) {
if (!getSignature(ErrorLoc, Inst.getOperand(OpIdx++),
wasm::WASM_SYMBOL_TYPE_TAG, Sig))
- SentTypes.insert(SentTypes.end(), Sig->Params.begin(),
- Sig->Params.end());
+ llvm::append_range(SentTypes, Sig->Params);
else
Error = true;
}
|
Member
|
@llvm/pr-subscribers-backend-webassembly Author: Kazu Hirata (kazutakahirata) ChangesFull diff: https://github.com/llvm/llvm-project/pull/135568.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 6bf6ce7167833..68218e59961c2 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -3980,7 +3980,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
}
if (!InsertBeforeLR)
- CSI.insert(CSI.end(), VGSaves.begin(), VGSaves.end());
+ llvm::append_range(CSI, VGSaves);
}
Register LastReg = 0;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 356040da95672..bd95bcd89e183 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4055,8 +4055,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
}
if (IsChainCallConv)
- Ops.insert(Ops.end(), ChainCallSpecialArgs.begin(),
- ChainCallSpecialArgs.end());
+ llvm::append_range(Ops, ChainCallSpecialArgs);
// Add argument registers to the end of the list so that they are known live
// into the call.
@@ -15526,9 +15525,9 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// Adjust the writemask in the node
SmallVector<SDValue, 12> Ops;
- Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
+ llvm::append_range(Ops, Node->ops().take_front(DmaskIdx));
Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
- Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
+ llvm::append_range(Ops, Node->ops().drop_front(DmaskIdx + 1));
MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
index ec11a78f8a7af..9d35626f449de 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
@@ -14,6 +14,7 @@
#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include <cstddef>
#include <cstdint>
@@ -60,7 +61,7 @@ class UnwindOpcodeAssembler {
/// Emit unwind raw opcodes
void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) {
- Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end());
+ llvm::append_range(Ops, Opcodes);
OpBegins.push_back(OpBegins.back() + Opcodes.size());
}
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
index 156b40eb43a3e..68b24dbe9f006 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
@@ -55,7 +55,7 @@ void WebAssemblyAsmTypeCheck::funcDecl(const wasm::WasmSignature &Sig) {
void WebAssemblyAsmTypeCheck::localDecl(
const SmallVectorImpl<wasm::ValType> &Locals) {
- LocalTypes.insert(LocalTypes.end(), Locals.begin(), Locals.end());
+ llvm::append_range(LocalTypes, Locals);
}
void WebAssemblyAsmTypeCheck::dumpTypeStack(Twine Msg) {
@@ -357,8 +357,7 @@ bool WebAssemblyAsmTypeCheck::checkTryTable(SMLoc ErrorLoc,
Opcode == wasm::WASM_OPCODE_CATCH_REF) {
if (!getSignature(ErrorLoc, Inst.getOperand(OpIdx++),
wasm::WASM_SYMBOL_TYPE_TAG, Sig))
- SentTypes.insert(SentTypes.end(), Sig->Params.begin(),
- Sig->Params.end());
+ llvm::append_range(SentTypes, Sig->Params);
else
Error = true;
}
|
kuhar
approved these changes
Apr 13, 2025
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